1. The Field of the Invention
The present invention relates to the manufacture of semiconductor devices. More particularly, the present invention is directed to novel processes for forming self-aligned polyplugs having large contact areas.
2. The Relevant Technology
FIG. 1 is a flow diagram of selected steps of a conventional process flow for producing DRAM circuits on a silicon substrate, which steps are relevant to the present invention.
At the beginning of the process flow of FIG. 1, silicon wafers have already been processed to the point that gate structures of the DRAM circuits are formed upon the substrate. Nitride is then deposited in the first process step to enclose the gate structures. In the second step, the nitride layer is vertically anisotropically etched to leave only the vertical portions of the layer. In the third step, a thin layer of nitride is redeposited over the gate structures and the substrate.
According to the fourth step of the process flow of FIG. 1, a borophosphorous silica glass (xe2x80x9cBPSGxe2x80x9d) layer is then deposited on the surface of the wafer and flowed or densified to fill the surface features of the wafer. The BPSG forms a dielectric planarization layer. Upon the resulting relatively flat BPSG surface, a plug mask in the form of a patterned photoresist layer is produced in the fifth step using standard photolithography techniques. The resist layer is patterned to shield those areas in which no polysilicon plug is to be formed. In the sixth step, a vertical anisotropic BPSG etch removes the BPSG not vertically shielded by the patterned photoresist layer. In the seventh step, a vertical anisotropic nitride etch removes the nitride layer deposited in the third step, so that the polysilicon plugs can contact the source/drain regions. In the eighth step, the patterned photoresist layer is removed from the wafer.
In the ninth step of the process flow of FIG. 1, doped polysilicon is deposited upon the wafer surface to fill the areas left open by the BPSG and nitride etches. In the tenth step, the polysilicon on the wafer surface is gradually removed from the top downward by chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d), or dry etch-back, to leave poly plugs only.
FIG. 2 shows a portion of a typical cross section of a partially formed DRAM device after processing through step 5 of the process of FIG. 1.
With reference to FIG. 2, three gate stacks 20a, 20b, 20c have been formed upon a silicon substrate 10. Gate stack 20a includes a doped polysilicon gate 24a topped with tungsten silicide 26a and a thick nitride layer 27a. Polysilicon gate 24a is separated from silicon substrate 10 by gate oxide 22a. The components of the gate stacks 20b, 20c are as described with respect to the like numbered components of gate stack 20a. 
Gate stacks 20a, 20b, 20c are enclosed laterally by nitride spacers 28, which have been formed by nitride deposition followed by an anisotropic nitride etch. A second, thin layer nitride deposition has produced nitride film 29. A BPSG layer 30 has been deposited on and flowed over nitride film 29. A patterned photoresist layer 32 has been formed on BPSG layer 30 by photolithography techniques.
FIG. 3 shows the cross section of FIG. 2 after processing through step 6 of the process of FIG. 1, where step 6 is an anisotropic etch of the BPSG layer. The anisotropic BPSG etch has good selectivity of the BPSG layer 30 against the nitride of film 29, leaving nitride film 29 intact with little or no etching thereof, while removing the portions of BPSG layer 30 not shielded by the photoresist.
FIG. 4 shows the cross section of FIG. 3 after processing through steps 7 and 8 of the process of FIG. 1, an anisotropic nitride etch and a photoresist strip. The nitride covering gates 24a, 24b, 24c, is shown for convenience as an undifferentiated nitride layer 31. The anisotropic nitride etch has uncovered source/drain contact regions 34, 36, 38, 40 in silicon substrate 10, and etched small steps 42 into nitride layer 31 covering gates 24a and 24c. Patterned photoresist layer 32 has been removed by the photoresist strip.
FIG. 5 shows the cross section of FIG. 4 after doped polysilicon plug fill and chemical mechanical polishing (CMP) or dry etch-back to a first depth in accordance with steps 9 and 10 or 10A of the process of FIG. 1. Polyplugs 44, 46, 48 have been formed. The CMP or dry etch-back has been applied long enough to isolate plugs that should be isolated according to the circuit layout, but short enough to permit, where desired, local interconnect across gates, such as with polyplug 46 which interconnects across gate 24b. The top surfaces of polyplugs 44, 46, 48, respectively, constitute landing pads 50, 52, 54 for metal contact by a subsequent metalization layer or for contact by other subsequent contact or interconnect layers.
FIG. 6 shows an alternative cross section of FIG. 5 processed according to steps 9 and 10 of the process of FIG. 1, but with the CMP or dry etch-back step performed to a second depth greater than the first depth of FIG. 5. This second depth extends to the level of the top of nitride layer 31. Polyplugs 56, 58, 60, 62 are formed having, respectively, landing pads 64, 66, 68, 70.
CMP or dry etch-back to the second depth seen in FIG. 6 has certain advantages over CMP or dry etch-back stopping at the first depth seen in FIG. 5. First, CMP or dry etch-back to the second depth results in polyplugs having landing pads which are self-aligned with the nitride-enclosed gate structures. Second, a major goal of CMP or dry etch-back is to provide a precisely planarized surface for subsequent processing steps. CMP to the second depth improves the flatness of the polished surface above that of typical CMP because nitride layer 28 polishes away at a much slower rate than both BPSG layer 30 and the doped polysilicon material which forms the polyplugs. Thus polishing is slowed in those areas in which the nitride is reached earliest, resulting in a more even polishing compared to polishing that extends only to the first depth seen in FIG. 5.
The advantages of polishing to the second depth seen in FIG. 5 are tempered by the disadvantages of the small size of landing pads 64, 66, 68, 70. Small landing pads increase the criticality of subsequent alignment steps. A contact etch generally etches both nitride and oxide, so that any misalignment can result in contacts which short between source/drain regions and gates/wordlines. Small landing pad areas also increase the resistance at the contact material/doped polysilicon interface. It would thus be a significant advance to provide the advantages of CMP to the second depth seen in FIG. 6 without the inherent disadvantages of small landing pads.
Even where CMP or dry etch-back is performed only to the first depth shown in FIG. 5, large landing pads do not result if the width of the gate stacks is already at the limit of the resolution of the photolithography system employed. At the resolution limit, the line width of patterned photoresist layer 32 is as shown by outline O in FIG. 2. As seen in FIG. 2, the line width of patterned photoresist layer 32 at the resolution limit approaches the width of gate stacks 20a, 20b, 20c. This results in narrower polyplugs, shown in FIG. 5 by outline N, having smaller landing pads, even with CMP or dry etch-back only to the first level shown in FIG. 5. For gates or wordlines at the resolution limit, a method to increase the size of contact plug landing pads is thus needed, regardless of whether CMP to the second depth shown in FIG. 6 is employed.
An object of the present invention is to provide source/drain contact plugs having large landing pad areas which are self-aligned to adjacent gates.
Another object of the present invention is to create self-aligned source/drain contact plugs having large landing pad areas in relatively few process steps.
Another object of the present invention is to improve the flatness of surfaces produced by CMP.
Another object of the present invention is to increase yield by decreasing the criticality of mask alignment subsequent to completion of source/drain contact plugs.
Another object of the present invention is to allow for smaller minimum feature size by increasing the size of landing pad areas of source/drain contact plugs.
In accordance with one presently preferred process of the present invention, transistors including gate/wordline stacks are formed upon a silicon substrate. Nitride is deposited over the gate/wordline stacks. The nitride is then etched to form nitride spacers enclosing the gates. The nitride etch process includes either a plasma sputter etch or a reactive ion etch with film-forming agents, such that facets are etched in the nitride at top corners of the gate/wordline stacks. Typical processing then follows, but with an optional isotropic etch of the plug mask layer to reduce the line width of the plug mask below the resolution limit of the photolithography system. The facets on the nitride spacers at the top corners of the gate/wordline stacks result in a polyplug having a wider landing pad area, even if CMP or dry etch-back is performed down to a depth of the top of the nitride spacers.
In accordance with another presently preferred process of the present invention, conventional processing is varied by an optional isotropic etch of the plug mask layer to reduce the line width of the plug mask below the resolution limit of the photolithography system, if needed, and by replacing a conventional anisotropic BPSG etch step with a step that both anisotropically etches BPSG and facet-etches the nitride enclosing the gate/wordline stacks. The resulting facets on the nitride spacers at the top corners of the gate/wordline stacks, after further processing, result in a polyplug having a wider landing pad area, even if CMP or dry etch-back is performed down to the nitride.
In accordance with yet another presently preferred process of the present invention, conventional processing is varied by isotropically etching the plug mask layer after it has been patterned, decreasing the effective line width of the plug mask layer. Subsequent standard processing results in wider polyplug landing areas if CMP or dry etch-back is performed down to a level above the top of the nitride. Alternatively, a step feature may be etched in the nitride at the corners of the gate/wordline stacks, which nitride at the corners of the gate/wordline stacks is left exposed after the BPSG etch. Isotropic etching of the plug mask may optionally be used to increase the area of nitride exposed at the corners of the gate/wordline stacks after the BPSG etch. Subsequent processing then results in wider polyplug landing areas even with CMP or dry etch-back performed down to the nitride enclosing the gate/wordline stacks.
In accordance with an additional presently preferred process of the present invention, conventional transistor structures including gate/wordline stacks and source/drain regions are formed upon a silicon substrate, and the gate/wordline stacks are enclosed in nitride spacers. A thin nitride layer is deposited over the entire surface. BPSG is then deposited over the entire surface and densified. A first CMP is then performed down to the level of the nitride enclosing the gate/wordline stacks, producing a flat surface. On the flat surface produced by the first CMP, a patterned plug mask layer is formed. The BPSG left exposed by the plug mask layer is then removed by an anisotropic etch. The plug mask layer is then optionally isotropically etched to increase the area left exposed thereby. The nitride layers left exposed are then anisotropically etched, removing a portion of the nitride at the top corners of the gate/wordline stacks and removing the nitride over the source/drain regions. Subsequent polyplug fill and CMP or dry etch-back down to the nitride result in wider polyplug landing areas and self-aligned polyplugs.
These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.